Job Description
Summary: ForwardEdge ASIC is seeking skilled and detail-oriented Design-for-Test (DFT) Engineer to join our talent network. As a DFT Engineer, you will play a pivotal role in our semiconductor design team, focusing on the physical implementation of advanced ASIC designs. You will work closely with architecture, RTL, Logic design, Verification and Test & Validation teams to ensure high-performance, ASIC designs are successfully implemented and delivered to production.
- Drive ASIC designs through DFT techniques and features such as compressed scan, BIST, Boundary Scan covering digital logic domain and embedded memories. Collaborate with logic, verification, manufacturing, and test engineers to develop test plans.
- Well versed in JTAG with expertise in DFT RTL/gate level insertion, ATPG, coverage analysis, stuck-at, zero-delay/SDF-based pattern simulation.
- Ensure specification compliance, quality, performance, and manufacturing yield are maintained. Analyze/debug ATPG patterns through simulations on RTL or gate-level netlist models, follow-up with manufacturing and test engineering to ensure proper operation on actual hardware. Analyze expected/actual variances to determine root cause and correct.
- Proficient in verilog, logic design and scripting-languages (tcl, python, csh/bash).
- Self-Motivated and forward-Looking individual who embraces team-oriented approaches to create and verify DFT solutions. Low-pin count DFT solutions and techniques is a plus.
- Work with all process node technology with various ASIC Fabs experience with Industry-Leading EDA DFT toolsets (Tessent, TestMax, or Modus, Verdi).
Qualifications: - Bachelor’s degree in electrical engineering, or a related field with 3-7 years experiences. More experienced candidates will be considered for senior physical design roles.
- Understanding of ASIC design principles, architectures, and semiconductor manufacturing processes.
- Excellent problem-solving skills and ability to work effectively in a dynamic team environment.
- Clearance: This position requires a US government security clearance. As such, US citizenship is required.
Nice to Have: - Master’s degree in electrical engineering, or a related field.
Work Environment: The work environment for this role typically involves a combination of office-based activities and collaboration with analog design, CAD, and physical verification teams. Occasional travel may be required for project meetings or customer engagements.
Benefits: - Work-life balance: Flexible 9/80 Work schedules with every other Friday off, hybrid work with primary location being in St. Paul, MN
- Competitive benefit package : Including options for healthcare and medical coverage, 401K Retirement Benefits with company contribution, as well as a generous holidays and PTO allotment. Selected candidate may also be eligible for short -term and long-term incentives.
Note: This requisition is designed to cultivate a talent pipeline for both present and future opportunities within our organization. We are proactively seeking qualified candidates to ensure a continuous flow of talent. Your application will be considered for upcoming positions within our company.
Job Tags
Holiday work, Full time, Temporary work, Flexible hours,